1. Field of the Invention
The present invention generally relates to the field of semiconductor manufacturing and, more particularly, to a Wafer Level Package (WLP) with improved interconnection reliability and a method for manufacturing the same.
2. Description of the Related Art
In order to meet packaging requirements for newer generations of electronic products, efforts have been expended to create reliable, cost-effective, small, and high-performance packages. Such requirements are, for example, reductions in electrical signal propagation delays, reductions in overall component area, and broader latitude in input/output (I/O) connection pad placement.
To meet these requirements, a WLP has been developed, wherein an array of external I/O terminals is distributed over the semiconductor surface, rather than just located at one or more chip edges as in a conventional peripheral-leaded package. Typically, an array of solder balls provide the connection means between electrical signals of corresponding external connection pads and the WLP I/O terminals. Such distribution of terminal locations reduces the need for embedding signal lines that connect electrical circuit blocks of an integrated circuit (IC) to edge-located I/O terminal connection pads. Elimination of such signal lines improves the electrical performance of the device, since such lines typically have an associated high capacitance. Further, the area occupied by the IC with interconnections when mounted on a printed circuit board or other substrate is merely the size of the chip, rather than the size of a packaging leadframe. Thus, the size of the WLP may be made very small.
FIG. 1 illustrates a cross-sectional view of a conventional Ball-Grid-Array (BGA) interface structure. A chip 10 having a connecting pad 20 is attached to a substrate or printed circuit board (PCB) 50 by a solder ball 40. A significant disadvantage of such a connection means, however, is that the metallic solder balls 40 are minimally elastic. A junction between connecting pad 20 and solder ball 40 is indicated by shaded area 30. Shaded area 30 is of the same material as solder ball 40 and is shown as a distinct element for explanation purposes only in order to show the subsequent effects of cracks and non-resilient stresses that can result from divergent movements between chip 10 and PCB 50.
FIGS. 1b and 1c illustrate cross-sectional views of the conventional interface structure shown in FIG. 1a during various stages of thermal cycling, i.e., heat up and cool down, respectively, to show vertical movement and the forces that act on a solder connection as a result of the expansion and contraction;
Referring to FIG. 1b, under thermal changes that are normally associated with typical operation of an electronic device, a significant mismatch between the coefficient of thermal expansions (CTE) between the chip 10 and the epoxy-glass printed circuit board 50 can cause mechanical stress on the solder connection at junction 30. In other words, when the chip heats up during use, both the chip and the board expand at different rates, which can produce the distortion shown in FIG. 1b. When the heat is removed, both the chip and the substrate shrink at different rates as shown in FIG. 1c. The relative expansions and contractions stress the rigid interconnections, i.e., the solder balls. Such expansion/contraction differential become more pronounced for larger chip sizes, with peripheral areas of the chip exhibiting significantly larger expansion than that of a center portion of the chip.
As can be readily seen, as one or the other opposing sides of the solder connection move, such as during the aforementioned thermal expansion and contraction, a torquing can be seen on solder ball 40 and joint 30. Typically, with repeated expansion and contraction at temperatures that are below the melting point of the solder, rigid joint 30 can be stressed sufficiently to cause separation or cracking from pad 20 as indicated by the area labeled 32 in FIG. 1c, thereby damaging the reliability of the solder connection
Thus, there is a demonstrated need for a WLP having improved interconnection reliability, especially between the chip and the PCB, and a method of manufacturing the same.